With shrinking dimensions of various integrated circuit components, transistors such as FETs have experienced dramatic improvements in both performance and power consumption. These improvements may be largely attributed to the reduction in dimensions of components used therein, which in general translate into reduced capacitance, resistance, and increased through-put current from the transistors. Nevertheless, performance improvement brought up by this type of “classic” scaling, in device dimensions, has recently met obstacles and in some cases even been challenged, when the scaling goes beyond a certain point, by the increase in leakage current and variability that are inevitably associated with the continued reduction in device dimensions. Planar transistors, such as metal oxide semiconductor field effect transistors (MOSFETs) are particularly well suited for use in high-density integrated circuits. As the size of MOSFETs and other devices decreases, the dimensions of source/drain regions, channel regions, and gate electrodes of the devices, also decrease.
The design of ever-smaller planar transistors with short channel lengths makes it necessary to provide very shallow source/drain junctions. Shallow junctions are necessary to avoid lateral diffusion of implanted dopants into the channel, since such diffusion disadvantageously contributes to leakage currents and poor breakdown performance. Shallow source/drain junctions, with a thickness of about 30 nm to 100 nm, are generally required for acceptable performance in short channel devices. Silicon-on-insulator (SOI) technology allows the formation of high-speed, shallow junction devices. In addition, SOI devices improve performance by reducing parasitic junction capacitance.
In an SOI substrate, a buried oxide (BOX) film made of silicon oxide is formed on single crystal silicon, and a single crystal silicon thin film is formed thereon. Various methods of fabricating such SOI substrates are known, one of which is Separation-by-Implanted Oxygen (SIMOX), wherein oxygen is ion implanted into a single crystal silicon substrate to form a BOX film. Another method of forming an SOI substrate is wafer bonding, wherein two semiconductor substrates with silicon oxide surface layers are bonded together at the silicon oxide surfaces to form a BOX layer between the two semiconductor substrates.
Scaling CMOS devices has pushed the number of parameters out of a negligible region to the point of becoming a significant circuit design factors. One of the important device parameters is the short-channel control and Extremely thin Silicon-On-Insulator (ETSOI), both becoming a new class of transistors designed for this propose. ETSOI, a fully depleted charge carriers transistor device uses an ultra-thin silicon channel wherein the majority carriers are fully depleted (FD) during operation.
The thickness of an ETSOI layer typically ranges from 3 nm to 20 nm. Due to the extremely thin SOI layer, the active SD and Extension regions experience create difficulties for dopant implants and activation annealing. Although implants can be conducted, only partial dopants are activated due to lack of silicon re-crystallization. The sheet resistance from both active regions is so elevated that its electrostatic performance is severely degraded.
Scaling of CMOS, particularly thin SOI devices, requires raised source/drain (S/D) to lower the external resistance. Conventional raised S/D comes with the drawback of increased parasitic capacitance between the raised S/D and the gate. Furthermore, in some device structure, for example, extremely thin SOI (ETSOI), the extension resistance becomes the dominant component of total external resistance. The extension resistance can be lowered by thickening the SOI in extension region as well. However, the trade-off has to be made between two competing requirements—lowering external resistance and minimizing the increase of parasitic capacitance.